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Altera_Forum's avatar
Altera_Forum
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15 years ago

ALTPLL constant output

Hi, I'm using a ATLPLL IP In my design. The PLL has one input clock, one areset, one Lock output and one output clock. The input clock is 50MHz . The PLL outputs should be 100MHz. I want the o...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Not in general.

Maybe that, if your frequency drift is fast enough and with a zero average value, the bandwidth of the PLL can filter it out.

Altera PLL have a programmable bandwidth that you can set to LOW to increase the rejection to input frequency changes.

This will affect your lock time however.

For a manual:

http://www.altera.com/literature/ug/ug_altpll.pdf