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Altera_Forum
Honored Contributor
Honored ContributorALTPLL constant output
Hi, I'm using a ATLPLL IP In my design. The PLL has one input clock, one areset, one Lock output and one output clock. The input clock is 50MHz . The PLL outputs should be 100MHz. I want the o...
Altera_ForumHonored Contributor
Honored ContributorI basically understood your point about a PLL being able to filter jitter. But I think, the ability of the Altera FPGA PLL to perform the same is rather limited, e.g. if you consult the allowable input jitter specification. Furthermore, it seems obvious, that this is not what the original poster intended, see the > 2 MHz variation requirement.
