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Altera_Forum's avatar
Altera_Forum
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15 years ago

ALTLVDS variable behaviour after reset

I'm using an altlvds_rx receiver in Cyclone III with external PLL. After a reset and finished alignment, it takes a variable number of (slow) clock periodes before getting valid data. That's weird, because at the input side nothing changes. What could be the cause of this variation?

See the attached jpg-file from signaltap:

align_reset @ sample 0

rx_in is the sync-pattern

rx_data is altlvds output

C0, C1, C2: fast clock, slow clock, read clock.

Valid data (which is 00000000000000000000000) occurs somewhere between sample 375 and 801, depending on......... I don't know.

Cheers, Ton

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    A reply to myself (and anybody else interested).

    The variable data latency is due to the buffer implementation.

    I used RAM buffer, because that was default and used the least resources.

    Now I tried MUX and LE and they both give a FIXED latency of 3 slow clock periods.

    Seems like a bug in the RAM buffer implementation. I implemented several workarounds for this in the past weeks, but was never satisfied with it.

    I'm glad I solved the issue but frustrated about this bug and lack of information conserning buffer implementation.

    Cheers, Ton