Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

ALTLVDS variable behaviour after reset

I'm using an altlvds_rx receiver in Cyclone III with external PLL. After a reset and finished alignment, it takes a variable number of (slow) clock periodes before getting valid data. That's weird, b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

A reply to myself (and anybody else interested).

The variable data latency is due to the buffer implementation.

I used RAM buffer, because that was default and used the least resources.

Now I tried MUX and LE and they both give a FIXED latency of 3 slow clock periods.

Seems like a bug in the RAM buffer implementation. I implemented several workarounds for this in the past weeks, but was never satisfied with it.

I'm glad I solved the issue but frustrated about this bug and lack of information conserning buffer implementation.

Cheers, Ton