altlvds_rx

I am trying to simulate an Arria V altlvds_rx mega-function using modelsim10.0c starter edition.

From some reason in the simulation the rx_out port is always '0' and the rx_outclock port is always 'X'.

I am feeding the altlvds_rx with a self generated clock signal (" CLK <= not CLK after 5 ns;") and data.