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Altera_Forum's avatar
Altera_Forum
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13 years ago

ALTGX with clock comming form ALTCLKCTRL

Hi all,

I am trying to drive my ALTGX function with a clock coming from ALTCLKCTRL.

The aim of my project is to drive the transceiver module with different frequencies. For that i have create different PLL clocks with ATLPLL function, for trying to switch between them i have implemented the ALTCLKCTRL function, supplying the output clock of this function to the ALTGX block.

The compilation has gone ok, but some critical warnings are showing up:

Critical Warnings : (15042) , (15043) which are saying that the inclk of the transceiver is being drive by different specifies frequencies.

(15043): Input port inclk[0] of PLL "transceiver:t1|transceiver_alt_c3gxb:transceiver_alt_c3gxb_component|altpll:pll0|altpll_8b71:auto_generated|pll1" and its source clk[1] (the output port of PLL "the_pll:plls|altpll:altpll_component|the_pll_altpll:auto_generated|pll1") have different specified frequencies, 50.0 MHz and 100.0 MHz respectively

Also i am having some warnings that advice me about that the clock assignment (of the clock that drive the transceiver block) is being ignored.

My doubt is about if the thing i am trying to achieve (change the frequency that runs the transceiver) it is possible and if i should take care of this warnings.

here i let a picture of the RTL view.

Thanks in advance,

Lucia

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Lucia,

    From what i understood,

    The input clock of the ALTGX (GX Transceiver Megafunction) can only be driven by Global Clock pins, Using OTHER CLOCK SOURCES will result in DESIGN CONFLICT.

    The only option i think to drive/switch GX Transceiver between different clock frequencies is PLL Dynamic Reconfiguration.

    Regards,

    Swami.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks for the quick reply.

    Yes, use PLL reconfiguration is another of the options that i had in mind, but i think is more complicated, that's why im trying this one first. But, as you have said it may not work, actually some warnings are showing up about that the transceiver clock is not being drive with the correct clocks.

    Making PLL reconfiguration i am having some problems. I dont know how to connect everything. I mean i dont know how to connect the different ROM's with the different .mif files. I have seen that it is an example in the ALTPLL_RECONFIG but it is not clear enough. In that example they are connecting the ALTPLL_RECONFIG blobk with ALTPLL function.

    Do you have any clue of how to connect eveything?

    Thanks in advance.

    Lucia
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Lucia,

    I took "an507_de1_display" design as an example and tried with cyclone4 device.

    Try Application note: "AN 507: Implementing PLL Reconfiguration in Cyclone III Devices"

    check out the example design "an507_de1_display". You'll get more idea about connecting ROMs to .mif files.

    Please keep me updated if you find a solution for the PLL reconfiguration with GX Transceivers. Thank you.

    Regards,

    Swami.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Swami,

    Thanks for the advise you gave me. I took a look on the document you told me , and yes it is showing clearly how it is connected the Rom blocks with the mux.

    But i have seen that this example is about how to generate different .mif files for using them with ALTPLL Megafunction.

    After reading that document, my doubts now are the next ones.

    It is possible to implement the same design but instead of using ALTPLL function use ALTGX???

    How to connect the clock of ALTGX?, becausse the clock that is running the transceiver (ALTGX) is std_logic_vector (0 downto 0) and the one generated by ALTPLL_RECONFIG is std_logic?

    I have been reading and i have found another examples that maybe are of your interest:

    - "Implementing Dynamic Reconfiguration in Cyclone IV Device" : in the page 14 is an explanation of how to create .mif files, but now for using them with ALTGX.

    - "ALTPLL_RECONFIG manual" : example of how to generate different pll's (similar to the one you told me)

    Thanks,

    Regards,

    Lucia
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Lucia,

    it is possible to implement the same design but instead of using altpll function use altgx???

    Yes, I this, but the when you connect ALTGX Megafunction and enable PLL dynamic reconfiguration, it doesn't generate the desired .mif file. This is where i am stuck now..

    how to connect the clock of altgx?, becausse the clock that is running the transceiver (altgx) is std_logic_vector (0 downto 0) and the one generated by altpll_reconfig is std_logic?

    Connect clock port of ALTPLL_RECONFIG to fpga or pll clock freq. (25Mhz - 50Mhz)

    Connect clock port of ALTGX to the physical clock port (from a dedicated oscillator from the FPGA board)

    Hope this helps.. Thanks for your inputs.. I will check the manuals..

    Regards,

    Swami.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Swami,

    I will try your advises and i will tell you how its going, thank you so much.

    but, when you are saying

    "Connect clock port of ALTGX to the physical clock port (from a dedicated oscillator from the FPGA board)"

    you mean the calibration clock? or you mean the pll_inclk, because if its the pll_inclk i think that it must be driven by the ALTGX_RECONFIG function.

    For generating the .mif files : have you enable the option of the menu Assigments => Settings??

    if not, for generating mif files from ALTGX you need to enable the option "Generate GXB Reconfig MIF", for doing it, enter in the menu Assignments, then Settings and choose the option "Fitter Settings", then select more settings and just write an ON in the option "Generate GXB Reconfig MIF"

    I hope i helped you.

    Thanks,

    regards,

    lucia
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Swami,

    I made a mistake when i was writing the thread.

    Each time is written altgx_reconfig i was meaning ALTPLL_RECONFIG. Sorry for the mistake.

    So the therad in which i asked about how to connect the clocks, i was meaning how to connect the input pll_inclk of the ALTGX, cause it is supposed that is the one we want to control with pll reconfinguration.

    sorry and thanks

    regards,

    lucia