Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHi Lucia,
it is possible to implement the same design but instead of using altpll function use altgx??? Yes, I this, but the when you connect ALTGX Megafunction and enable PLL dynamic reconfiguration, it doesn't generate the desired .mif file. This is where i am stuck now.. how to connect the clock of altgx?, becausse the clock that is running the transceiver (altgx) is std_logic_vector (0 downto 0) and the one generated by altpll_reconfig is std_logic? Connect clock port of ALTPLL_RECONFIG to fpga or pll clock freq. (25Mhz - 50Mhz) Connect clock port of ALTGX to the physical clock port (from a dedicated oscillator from the FPGA board) Hope this helps.. Thanks for your inputs.. I will check the manuals.. Regards, Swami.