Altera newby wants to ask some Questions

you can use HDL ( Hardware Design Language )

there are two famous languages such as VerilogHDL and VHDL.

when you install QuartusII(Altera's software).

some samples are installed with QuartuII.

so you can find HDL samples.

good luck.

:)

Thank you for the information I think I can Use HDL.

LG steve

:D

An advice:

Do not use Verilog.

Use SystemVerilog or VHDL.

And could you please tell me the difference between those programms?

Maybie you could tell me a good site where i can see some finished programms with these HDL languages.

VHDL is a strongly typed and very verbose language which makes you type *a lot* to get anything done

Verilog is pretty much the oposite, which gets things done with much less typing but will ocasionally bite you when you're not looking.

SystemVerilog extends and refines Verilog.

All that said, these languages are not programming languages. They are Hardware Description Languages which describe the behaviour of digital systems.

You need a decent understanding of digital systems and of how HDL is mapped to FGPA logic to get anything done.

Examples:

http://www.vhdl.org/vhdlsynth/vhdlexamples/test_counter.vhdl

http://www.asic-world.com/examples/verilog/simple_counter.html#8-bit_simple_up_counter

rbugalho I have professional experience with both VHDL (8 years) and SystemVerilog (2 years).

And I must say I disagree: VHDL is sometimes a bit verbose, but there is no need to type a *lot*. In some situations you actually type less in VHDL than in SystemVerilog.

For me the worst is Verilog, it is really a *lot* more verbose than both SystemVerilog and VHDL.

Steve_ld, just pick a couple of books from the library and use Google, you will get some nice tutorials.

To put together simple systems, you don't _need_ to know any HDL. Just read up on SOPC Builder. Odds are that at least for initial systems it will be enough.

Be warned, System Verilog is like an all you can eat buffet. Lots of options can mean anything from a pleasant experience to serious indigestion...

Cheers,

--slacker

Here is a research paper that I suggest:

http://class.ee.iastate.edu/ee465/ee465s02/notes/billfuchs.pdf

VHDL was developed by the United States Department of Defense specifically to help mediate the obsolescence of hardware components. The DOD eventually turned over the rights to VHDL to the IEEE in hopes that it would gain acceptance and investment in the public/private sector. If you are going to be doing government work, you will find the VHDL is almost always mandated.

Verilog on the other hand grew out of the public sector and actually was owned by several private companies. Cadence was the last official owner of the language. Most companies in the private sector latched onto Verilog. Cadence eventually made the language open for fear that VHDL (being open by that time) would overtake Verilog in acceptance. Eventually IEEE essentially took over Verilog in order to standardize it to avoid independent implementations of the language.

Verilog is very C-like in it's syntax. It has a much lower learning curve than VHDL. I will disagree with amilcar and state the VHDL is more verbose than Verilog. However, the verbosity allows for doing some things in VHDL that can't be done directly in Verilog.

Jake

I suspect the OP comes from a programming background, so let me put it like this:

if one compares Verilog to C, then SystemVerilog would be C++ and VHDL would be ADA.