Altera newby wants to ask some Questions

rbugalho I have professional experience with both VHDL (8 years) and SystemVerilog (2 years).

And I must say I disagree: VHDL is sometimes a bit verbose, but there is no need to type a *lot*. In some situations you actually type less in VHDL than in SystemVerilog.

For me the worst is Verilog, it is really a *lot* more verbose than both SystemVerilog and VHDL.

Steve_ld, just pick a couple of books from the library and use Google, you will get some nice tutorials.