Altera newby wants to ask some Questions

VHDL is a strongly typed and very verbose language which makes you type *a lot* to get anything done

Verilog is pretty much the oposite, which gets things done with much less typing but will ocasionally bite you when you're not looking.

SystemVerilog extends and refines Verilog.

All that said, these languages are not programming languages. They are Hardware Description Languages which describe the behaviour of digital systems.

You need a decent understanding of digital systems and of how HDL is mapped to FGPA logic to get anything done.

Examples:

http://www.vhdl.org/vhdlsynth/vhdlexamples/test_counter.vhdl

http://www.asic-world.com/examples/verilog/simple_counter.html#8-bit_simple_up_counter