Altera newby wants to ask some Questions

Here is a research paper that I suggest:

http://class.ee.iastate.edu/ee465/ee465s02/notes/billfuchs.pdf

VHDL was developed by the United States Department of Defense specifically to help mediate the obsolescence of hardware components. The DOD eventually turned over the rights to VHDL to the IEEE in hopes that it would gain acceptance and investment in the public/private sector. If you are going to be doing government work, you will find the VHDL is almost always mandated.

Verilog on the other hand grew out of the public sector and actually was owned by several private companies. Cadence was the last official owner of the language. Most companies in the private sector latched onto Verilog. Cadence eventually made the language open for fear that VHDL (being open by that time) would overtake Verilog in acceptance. Eventually IEEE essentially took over Verilog in order to standardize it to avoid independent implementations of the language.

Verilog is very C-like in it's syntax. It has a much lower learning curve than VHDL. I will disagree with amilcar and state the VHDL is more verbose than Verilog. However, the verbosity allows for doing some things in VHDL that can't be done directly in Verilog.

Jake