--- Quote Start ---
module test_rs232(input CLOCK_50, output [17:0] LEDR, output UART_TXD, input UART_RXD, input [1:0] KEY);
wire reset;
assign reset = ~KEY[0];
parameter DATA_WIDTH = 8;
wire [DATA_WIDTH-1:0] received_data;
wire [DATA_WIDTH-1:0] transmit_data;
wire transmitting_data;
wire receiving_data, data_received;
wire transmit_data_en;
RS232_In u3(.clk(CLOCK_50), .reset(reset), .serial_data_in(UART_RXD), .receive_data_en(1'b1), .received_data(received_data),
.data_received(data_received), .receiving_data(receiving_data));
assign LEDR[7:0] = received_data;
endmodule
//RS232_In.v
module RS232_In (
// Inputs
input clk,
input reset,
input serial_data_in,
input receive_data_en,
// Outputs
output reg [(DATA_WIDTH-1):0] received_data,
output reg receiving_data,
output reg data_received,
output baud_clock
);
parameter BAUD_COUNT = 9'd434;
parameter DATA_WIDTH = 8;
parameter TOTAL_DATA_WIDTH = DATA_WIDTH + 2;
wire shift_data_reg_en;
wire all_bits_received;
assign baud_clock = shift_data_reg_en;
reg [(TOTAL_DATA_WIDTH - 1):0] data_in_shift_reg;
//reg receiving_data;
reg prev_receiving_data;
always @(posedge clk)
begin
if (reset == 1'b1)
receiving_data <= 1'b0;
else if (all_bits_received == 1'b1)
receiving_data <= 1'b0;
else if (serial_data_in == 1'b0)
receiving_data <= 1'b1;
end
always @(posedge clk)
begin
prev_receiving_data <= receiving_data;
if (receiving_data==1'b1)
data_received <= 1'b0;
else if (prev_receiving_data==1'b1)
begin
data_received <= 1'b1;
received_data <= data_in_shift_reg[DATA_WIDTH:1];
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_in_shift_reg <= {TOTAL_DATA_WIDTH{1'b0}};
else if (shift_data_reg_en)
data_in_shift_reg <=
{serial_data_in, data_in_shift_reg[(TOTAL_DATA_WIDTH - 1):1]};
end
Baud_Counter RS232_In_Counter (
// Inputs
.clk(clk),
.reset(reset),
.reset_counters(~receiving_data),
// Outputs
.baud_clock_rising_edge(),
.baud_clock_falling_edge(shift_data_reg_en),
.all_bits_transmitted(all_bits_received)
);
defparam
RS232_In_Counter.BAUD_COUNT= BAUD_COUNT,
RS232_In_Counter.DATA_WIDTH= DATA_WIDTH;
/*
Altera_UP_SYNC_FIFO RS232_In_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (all_bits_received & ~fifo_is_full),
.write_data (data_in_shift_reg[(DATA_WIDTH + 1):1]),
.read_en (receive_data_en & ~fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (received_data)
);
defparam
RS232_In_FIFO.DATA_WIDTH = DATA_WIDTH,
RS232_In_FIFO.DATA_DEPTH = 128,
RS232_In_FIFO.ADDR_WIDTH = 7;
*/
endmodule
module Baud_Counter (input clk, input reset, input reset_counters, output reg baud_clock_rising_edge, output reg baud_clock_falling_edge,
output reg all_bits_transmitted);
parameter BAUD_COUNTER_WIDTH = 9;
parameter BAUD_COUNT = 5;
parameter BAUD_TICK_COUNT = BAUD_COUNT - 1; //9'd433;
parameter HALF_BAUD_TICK_COUNT = BAUD_COUNT / 2; //9'd216;
parameter DATA_WIDTH = 9;
parameter TOTAL_DATA_WIDTH = DATA_WIDTH + 2;
reg [(BAUD_COUNTER_WIDTH - 1):0] baud_counter;
reg [3:0] bit_counter;
// control baud_counter
always @(posedge clk)
begin
if (reset == 1'b1)
baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};
else if (reset_counters)
baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};
else if (baud_counter == BAUD_TICK_COUNT)
baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};
else
baud_counter <= baud_counter + 1'b1;
end
// control baud_clock_rising_edge signal
always @(posedge clk)
begin
if (reset == 1'b1)
baud_clock_rising_edge <= 1'b0;
else if (baud_counter == BAUD_TICK_COUNT)
baud_clock_rising_edge <= 1'b1;
else
baud_clock_rising_edge <= 1'b0;
end
// control baud_clock_falling_edge signal
always @(posedge clk)
begin
if (reset == 1'b1)
baud_clock_falling_edge <= 1'b0;
else if (baud_counter == HALF_BAUD_TICK_COUNT)
baud_clock_falling_edge <= 1'b1;
else
baud_clock_falling_edge <= 1'b0;
end
// control bit counter
always @(posedge clk)
begin
if (reset == 1'b1)
bit_counter <= 4'h0;
else if (reset_counters)
bit_counter <= 4'h0;
else if (bit_counter == TOTAL_DATA_WIDTH)
bit_counter <= 4'h0;
else if (baud_counter == BAUD_TICK_COUNT)
bit_counter <= bit_counter + 4'h1;
end
// control all_bits_transmitted signal
always @(posedge clk)
begin
if (reset == 1'b1)
all_bits_transmitted <= 1'b0;
else if (bit_counter == TOTAL_DATA_WIDTH)
all_bits_transmitted <= 1'b1;
else
all_bits_transmitted <= 1'b0;
end
endmodule
--- Quote End ---
The code compiles but there is no ledr's turned on.
The code is from here
http://www.johnloomis.org/digitallab/rs232/rs232lab.qdoc.html#baud_counter.v http://imageshack.us/photo/my-images/528/img00276201111141211.jpg/ Please let me knoe if u guys see any problem
Honored Contributor
