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Altera_Forum's avatar
Altera_Forum
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17 years ago

ALT2GXB clock handling

Hi,

I want to use one ALT2GXB (8.0 Build 231 SP 1 SJ Web Edition) in PIPE mode for a single lane PCIe configuration (generated through MegaWizard Plugin Manager, of course) on a StratixII GX.

I'm using one REFCLK input of the transceiver block from the PCIe connection as a reference clock for the CMU (you can just select 100 MHz).

Furthermore I'm using an ALTPLL to generate 125 MHz and 62.5 MHz clocks for my design behind the ALT2GXB. The input clock of this PLL is NOT the REFCLK input of the transceiver block. I also can't use the CMU 125 MHz output clock (how to route output clock of alt2gxb to a pll (http://www.alteraforum.com/forum/showthread.php?t=2252&highlight=alt2gxb)).

I'm not quite sure about connecting the 125 MHz output of the PLL to the Tranceiver phase compensation buffers. Can I just do that without losing any data?

How should i know if the Transceiver side clock connected to the phase compensation buffer and my generated 125 MHz clock meet the 0 PPM requirement?

In the Stratix II Device Handbook Volume2 (SIIGX5V2-4.3) on 2-122 they suggest to use an additional phase compensation buffer with the standard configuration - so i guess thats without using any of the rx/tx_coreclk inputs.

My question now is, how do i actually implement such a phase compensation buffer?

Another question is, if this phase compensation buffer should rather be a rate compensation buffer, because the problem of not knowing if the 0 PPM requirement is met.

The only way I see is to implement a dual clock fifo (kind of rate compensation buffer). But with this fifo, what if the ALT2GXB side clock is always a bit faster than my generated 125 MHz clock. I cannot compensate this in any way, because I've got no symbols to delete to prevent a FIFO overflow.

Is there no chance to connect my clock domain with the clock domain of the ALT2GXB in a reasonable way?

I hope you got my point and can help me out of this mess.

Thanks,

Joki

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I haven't worked with PIPE, but have done other protocols. Does your protocol do any character insertion/deletion? This basically compensates for clocks that are slightly out of sync with the transmission data rate. The bottom line is that if there isn't a way to compensate for this, then the clock source that generates the data upstream has to be the clock source that recovers it, as two different clocks will always have a difference greater than 0 PPM.

    I thought there was a phase-comp FIFO in the hard IP, but it sounds like your protocol is going to have to use the recovered clock, since that has a 0 PPM difference. So if you connect your 125MHz clock to the output of the PCFIFO, you will lose data.

    Is everything running at half-rate after that, and your concern that you don't have a PLL to create the divided down clock? You could do a divide-by-two clock and then just transfer the incoming data down to that with a phase-comp FIFO. You might want to file a Service Request about driving the PLL with the recovered clock. I thought there was some way to do that but can't remember.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thank you for your answer.

    Indeed the PCIe protocol compensates clock differentces of +-300 ppm between the recovered sender and the local clock by character insertion/deletion in a so called 'elastic buffer' or rate compensation FIFO. This FIFO is implemented in the ALT2GXB block.

    There is also a phase compensation FIFO implemented in the ALT2GXB block, one for the RX and one for the TX path at the border to the PLD fabric.

    From my point of view, the difference between the rate and the phase compensation FIFO is, that the phase compensation FIFO has to be supplied with equal frequency clocks, which are shifted in phase but don't run each other over, so the FIFO never runs over.

    The ALT2GXB block can be configured to clock those hard wired phase compensation FIFOs with the 125 MHz clock from its own CMU on both sides, so this 125 MHz clock could be used to clock my design. But as you already mentioned, I want to clock my system with 62,5 MHz and it would be nice to drive a PLL with the ALT2GXB output clock. As far as I can see from the StratixII Device Handbook, this is not possible.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I ran into a similar problem. My thought was to input the PCIe refclk to an enhanced PLL. Output a 125MHz clock to the dedicated refclk input of the GXB. Generate an internal 125MHz clock and other needed frequencies. This way, you get 0PPM difference between your internal 125MHz and the 125MHz going to the dedicated refclk inputof the GXB. Not sure if this will meet your requirements but it should work.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi,

    i thought of that option too. The problem is, that I've got a hardware platform on which I cannot change the PCIe refclk input signals to different input pins and therefore cannot use this method.