ALT2GXB clock handling

Thank you for your answer.

Indeed the PCIe protocol compensates clock differentces of +-300 ppm between the recovered sender and the local clock by character insertion/deletion in a so called 'elastic buffer' or rate compensation FIFO. This FIFO is implemented in the ALT2GXB block.

There is also a phase compensation FIFO implemented in the ALT2GXB block, one for the RX and one for the TX path at the border to the PLD fabric.

From my point of view, the difference between the rate and the phase compensation FIFO is, that the phase compensation FIFO has to be supplied with equal frequency clocks, which are shifted in phase but don't run each other over, so the FIFO never runs over.

The ALT2GXB block can be configured to clock those hard wired phase compensation FIFOs with the 125 MHz clock from its own CMU on both sides, so this 125 MHz clock could be used to clock my design. But as you already mentioned, I want to clock my system with 62,5 MHz and it would be nice to drive a PLL with the ALT2GXB output clock. As far as I can see from the StratixII Device Handbook, this is not possible.