ALT2GXB clock handling

I haven't worked with PIPE, but have done other protocols. Does your protocol do any character insertion/deletion? This basically compensates for clocks that are slightly out of sync with the transmission data rate. The bottom line is that if there isn't a way to compensate for this, then the clock source that generates the data upstream has to be the clock source that recovers it, as two different clocks will always have a difference greater than 0 PPM.

I thought there was a phase-comp FIFO in the hard IP, but it sounds like your protocol is going to have to use the recovered clock, since that has a 0 PPM difference. So if you connect your 125MHz clock to the output of the PCFIFO, you will lose data.

Is everything running at half-rate after that, and your concern that you don't have a PLL to create the divided down clock? You could do a divide-by-two clock and then just transfer the incoming data down to that with a phase-comp FIFO. You might want to file a Service Request about driving the PLL with the recovered clock. I thought there was some way to do that but can't remember.