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3LionsCT's avatar
3LionsCT
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

Agilex Reset_Release no associated clock

Hi,

I wonder if anyone can help me with a Platform designer error while using the Agilex Reset release IP. I wanted to combine the nInit_done signal with a couple of external resets to make a global reset. I added the Agilex Reset release IP and I combined it with my external resets in a separate HDL module that I wrote (see attached). 

I now have a system_platform error telling me that the reset_release IP and my HDL module have to be on the same clock domain (see attached) and that the reset_release IP has no associated clock. 

Does anyone know how to associate a clock with the reset release IP? I have tried everything I can think of but no luck

Thanks

Configuration

3 Replies

  • kbrunham_altera's avatar
    kbrunham_altera
    Icon for New Contributor rankNew Contributor
    1 month ago

    Hi 3LionsCT,

    The reset release IP's ninit_done signal is asynchronous, so there is no associated clock. From your RTL, the reset you are generating also is asynchronous so when you make the reset source in your _hw.tcl you need to set SYNCHRONOUS_EDGES to none.

     

    Can you share the _hw.tcl for your global_reset IP?

    • 3LionsCT's avatar
      3LionsCT
      Icon for Occasional Contributor rankOccasional Contributor
      1 month ago

      Hi Kbrunham,

      Thanks for the reply. You are indeed correct, I had set the synchronous-edges incorrectly. I changed it and it removed the errors

      Thanks again

      • BoonBengT_Altera's avatar
        BoonBengT_Altera
        Icon for Moderator rankModerator
        4 hours ago

        Dear Customer,

        I'm glad that your issue is resolved. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

        Thank you for engaging with us!

        Best regards,
        Altera Technical Support