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3LionsCT's avatar
3LionsCT
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Agilex Reset_Release no associated clock

Hi, I wonder if anyone can help me with a Platform designer error while using the Agilex Reset release IP. I wanted to combine the nInit_done signal with a couple of external resets to make a global...
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kbrunham_altera's avatar
kbrunham_altera
Icon for New Contributor rankNew Contributor
2 months ago

Hi 3LionsCT,

The reset release IP's ninit_done signal is asynchronous, so there is no associated clock. From your RTL, the reset you are generating also is asynchronous so when you make the reset source in your _hw.tcl you need to set SYNCHRONOUS_EDGES to none.

 

Can you share the _hw.tcl for your global_reset IP?

  • 3LionsCT's avatar
    3LionsCT
    Icon for Occasional Contributor rankOccasional Contributor
    2 months ago

    Hi Kbrunham,

    Thanks for the reply. You are indeed correct, I had set the synchronous-edges incorrectly. I changed it and it removed the errors

    Thanks again

    • BoonBengT_Altera's avatar
      BoonBengT_Altera
      Icon for Moderator rankModerator
      1 month ago

      Dear Customer,

      I'm glad that your issue is resolved. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

      Thank you for engaging with us!

      Best regards,
      Altera Technical Support