Forum Discussion
Hi,
You can generate examples from CXL IP in the latest Quartus Pro 25.1.1, with new added M-series FPGA. PCIe and CXL are two different IPs in the tool. CXL IP requires a license and its user guide is restricted to NDA users only. Please contact your local Sales or Distributor for more info.
The most basic CXL type is Base HIP. The PIPE mode is for simulation only.
The CXL uses R-Tile so current example designs are available for below two dev kits. The M-series dev kit requires MCIO cable.
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agi027.html
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html
The CXL test is heavily relied on a dedicated software, even checking the LTSSM. So you basically don't need a protocol analyzer.
Regards,
Rong
Hi Rong,
Thanks for the details.
To clarify my goal: I want to use PIPE Direct to attach my own (soft) CXL controller implemented in the FPGA fabric to the R-Tile—i.e., not using Intel’s CXL IP and bypassing the hard PCIe/CXL stacks.
Could you please confirm whether this is hardware-feasible on Agilex (R-Tile)?
- Is there any hardware-exposed PIPE Direct interface on R-Tile beyond simulation-only?
- If yes, which development kit(s), documents/examples, and enablement (NDA/license) are required?
- If no, can you confirm there is no supported path to implement a soft CXL controller that directly drives R-Tile via PIPE Direct?
For context, I have a CXL-capable host available (no protocol analyzer). I’m also considering the M-Series DK with MCIO as you noted.
Appreciate your guidance.
Best regards,
Yeongmin Shin