AGILEX 7-I R-Tile PCIe Root port : Unsupported Request received after enumeration

Hello Rong,

Which signals do you not understand ?

The PCIe configuration is Gen3x4.

The following signals :

slow_clk

slow_clk_resetn

avs_reconfig_address(31:0)

avs_reconfig_read

avs_reconfig_readdata(7:0)

avs_reconfig_readdatavalid

avs_reconfig_write

avs_reconfig_writedata(7:0)

avs_reconfig_waitrequest

enable to configure registers in the PCIe IP configured as a Root por, mainly for PCIe Enumeration.

The following signals :

Tx_st0_sop

Tx_st0_eop

Tx_st0_hvalid

Tx_st0_hdr(127:0)

Tx_st0_dvalid

Tx_st0_data(127:0)

Tx_st1_sop

Tx_st1_eop

Tx_st1_hvalid

Tx_st1_hdr(127:0)

Tx_st1_dvalid

Tx_st1_data(127:0)

Tx_ready

Enable to send PCIe commands to the PCIe Target (SSD) ( config Write, config Read, Memory write, Memeory read, etc..)

The following signals :

Rx_st0_sop

Rx_st0_eop

Rx_st0_hvalid

Rx_st0_hdr(127:0)

Rx_st0_dvalid

Rx_st0_data(127:0)

Rx_st0_empty(1:0)

Rx_st1_sop

Rx_st1_eop

Rx_st1_hvalid

Rx_st1_hdr(127:0)

Rx_st1_dvalid

Rx_st1_data(127:0)

Rx_st1_empty(1:0)

Enables to receive PCIe commands from the PCIe Target (SSD) ( Completion with or without data, Memory write, Memeory read, etc..)

My question is :

What is wrong in my command sequence to get an unsupported request on the first read after my PCIe enumeration ?

Or, do I miss something to do ?

To answer to this question, you need to analyze my signal tap, on which you have all the accesses recorded included the Unsupoorted Request Completion.

On my side I do not see what is wrong.

Thanks for help.
Serge