Forum Discussion
RongY_altera
Contributor
10 months ago2) Can you detail what you mean by the PCIe Command Register ? What address ? in Root Port or in Target ?
-->PCIe configuration space offset 0x4. Check RP side. Bit 1 is for Memory Space Enable.
Regards,
Rong
Serge93
Occasional Contributor
10 months agoHello Rong,
Yes Bit 1 and Bit 2 are set to 1.
Have you read the Signal Tap I sent you ?
Thanks.
Serge