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FBuss2's avatar
FBuss2
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4 months ago
Solved

Agilex 7 HBM2E burst length

I noticed that I can use a burst length of 1 (arlen/awlen = 0). But the datasheet says "In BL8 mode, the HBMC supports only a burst length of 2 for write and read transactions. If you issue a burst l...
Core Logic
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 months ago

    Hi FBuss2 ,

     

    HBM2E operates with fixed internal burst lengths (BL4/BL8).

    In BL8 mode, each internal column access returns a full BL8 worth of data.

    A 1‑beat AXI write on a narrow port often forces read‑modify‑write internally; a 1‑beat read fetches a full internal BL8 but delivers only one byte on AXI.

    This is highly inefficient and can degrade throughput and increase power.

     

    Regards,

    Adzim

FBuss2's avatar
FBuss2
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3 months ago

And a related question: what is the max burst length? The port is 8 bits wide, but it doesn't work if I use a length greater than 64 in BL8 mode.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 months ago

Hi FBuss2,

 

Sorry for the delay to reply. I was OOO last week and not able to reply on time.

 

Can you provide the HBM2E IP setting that you configured?

 

Are you testing on a Agilex 7 M devkit or a custom board?

 

Did you used example design to run the test or used your own design?

 

Regards,

Adzim

  • FBuss2's avatar
    FBuss2
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    3 months ago

    Here are all the IP configurations of the project: https://frank-buss.de/tmp/ip.zip
    Mostly default settings for the HBM2E IP, just BL8 enabled. I'm using the IA-860m PCIe card, with my own design, based on the card vendor cardtest example. Quartus version is 25.3.1, with patch 1.02 installed.

    • AdzimZM_Altera's avatar
      AdzimZM_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 months ago

      Hi FBuss2,

       

      When running the test, what is the AXSIZE and AXLEN you used?

      Could be possible the test has cross 4KB boundary.

       

       

      Regards,

      Adzim

      • FBuss2's avatar
        FBuss2
        Icon for New Contributor rankNew Contributor
        3 months ago

        These are the settings:

        AWLEN / ARLEN = "00"
        AWSIZE / ARSIZE = "110"
        AWBURST / ARBURST = "01"
        AWPROT = "010"

        Here is an example running on the FPGA. I don't have SignalTap, so I wrote my own logger for it.

        Some cycles later the HBM signals back the bvalid, and I can also read it back successfully with 1 burst (arlen=0). Attached is the full waveform file, including the read.