Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA?

Hi,

I am building on top of the Agilex 5E GSRD design. My goal is not to use the HPS-side DDR for the FPGA accelerator data buffer. Instead, I want the data path to be:

1. ARM/HPS writes input data -> HPS2FPGA bridge -> FPGA-side DDR4 via EMIF_IO96B_DDR4COMP FPGA
2. IP reads input data from FPGA-side DDR4 FPGA.
3. IP computes and writes result back to FPGA-side DDR4 
4. ARM/HPS reads result back from FPGA-side DDR4 via HPS2FPGA

My current Platform Designer connection is roughly:

1. HPS hps2fpga master -> EMIF_IO96B_DDR4COMP AXI memory-mapped slave
2. FPGA accelerator memory port -> same EMIF_IO96B_DDR4COMP
3. EMIF pins -> external DDR4

The EMIF configuration and DDR4 pin assignments are matched carefully against the example design: /agilex5e_installer_package/examples/bts_emif/bts_ddr4_2b downloaded from the agilex5e installer package.

I also tested the original bts_ddr4_2b style flow in the example using:

JTAG -> pattern adaptor -> EMIF -> DDR4

and DDR4 read/write tests pass without errors. So the FPGA-side EMIF DDR4 calibration/pattern test appears to work.

However, when I try to access the same FPGA-side DDR4 from Linux on HPS through the HPS2FPGA bridge using devmem2, the access fails badly. For example, accessing the HPS2FPGA mapped address causes a bus error / fatal SError. One example log:

root@agilex5dka5e065bb32aes1:~# devmem2 0x40000000 w

/dev/mem opened. [ 1017.877669] SError Interrupt on CPU2, code 0x00000000be000011 -- SError [ 1017.877707] CPU: 2 PID: 791 Comm: devmem2 Not tainted 6.12.19-altera-g7b497655d942 #1 [ 1017.877717] Hardware name: SoCFPGA Agilex5 SoCDK (DT) ... [ 1017.877814] Kernel panic - not syncing: Asynchronous SError Interrupt ... Bus error

For comparison, I connected the same HPS2FPGA bridge to an on-chip memory in the FPGA fabric. Accessing that on-chip memory from HPS with devmem2 works correctly. So the HPS2FPGA bridge itself seems functional.

Current observations:

1. HPS2FPGA -> on-chip memory works.
2. JTAG -> pattern adaptor -> EMIF -> DDR4 works. 
3. EMIF calibration appears to pass.
4. HPS2FPGA -> EMIF DDR4 causes SError / bus error / Linux kernel panic.

Here is my current Platform Designer connection. In the screenshot, you can see that I copied over the EMIF-driving logic from the installer package. For emif_axi4, one connection goes to my IP’s memory port, and the other goes to the HPS hps2fpga interface, although that HPS connection is not shown in this screenshot.

Does anyone have any clues about what might be wrong here? Is this expected to work, or is this use case currently not supported, i.e. HPS reading/writing data directly to FPGA-side DDR through HPS2FPGA while an FPGA IP also accesses the same DDR through the EMIF AXI4 interface? If any additional files would be helpful, I can provide them.

Thank you in advance!