Forum Discussion

amsssss123's avatar
amsssss123
Icon for New Member rankNew Member
1 day ago

Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA?

Hi, I am building on top of the Agilex 5E GSRD design. My goal is not to use the HPS-side DDR for the FPGA accelerator data buffer. Instead, I want the data path to be: ARM/HPS writes input data -...
Configuration
Programmable Logic Device
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 hours ago

Hi amsssss123 

 

Could you also share a screenshot of the HPS block?

 

There are a thins that would need to check:

  • Is the h2f_reset signal connected to the hps2fpga_axi_reset signal?
  • Is the s0_axi4_clock_out connected to the hps2_fpga_axi_clock?
  • Could you add in a logic to check the s0_axi4_ctrl_ready before any R/W to the EMIF happen.