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New ContributorAgilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA?
Hi amsssss123
Yes the hps2fpga_clk and the hps2fpga_rst are referencing to the hps2fpga_axi_clock and hps2fpga_axi_reset mentioned.
For the EMIF Clock in the first screenshot it is shows the Access Mode of the EMIF is in Sync Mode with a clock out present, it should be connected to the hps2fpg_clk.
If it is in Async Access Mode both hps2fpg_clk and s0_axi4_clk should be connected to the same clock source.
New ContributorHi,
Thank you very much for your reply! I have attached the screenshot of the HPS block.
I checked my current design, and you are right, the two signals you mentioned were not connected. I also went through the documentation again, and it does say that the h2f_reset signal needs to be connected to the hps2fpga_axi_reset signal for proper bridge operation. I missed that before.
I do have a few follow-up questions:
- In my screenshot, the HPS block ports are named hps2fpga_clk and hps2fpga_rst. Are these the same as the hps2fpga_axi_clock and hps2fpga_axi_reset signals mentioned in the documentation and in your reply?
For the clock connection, if I connect the EMIF s0_axi4_clock_out to the hps2fpga_axi_clock, do I also need to move the related HPS-side AXI/control logic to the same s0_axi4_clock_out domain?
Currently, the HPS-side logic is connected to clk_100, which is 100 MHz. My understanding from the EMIF documentation is that s0_axi4_clock_out is one-quarter of the memory clock frequency, i.e. mem_CK / 4. Please correct me if I misunderstood this. Since the DDR frequency is currently 800 MHz, I assume the EMIF clock output should be around 200 MHz.
In that case, if only the HPS-to-FPGA AXI clock is changed to the EMIF clock output, the related HPS-side logic would no longer all be in the same clock domain. Would that be okay, or should all related HPS-side AXI/control logic also be moved to the EMIF clock domain.
Thank you for your help and support!
Regular ContributorHi amsssss123
Yes the hps2fpga_clk and the hps2fpga_rst are referencing to the hps2fpga_axi_clock and hps2fpga_axi_reset mentioned.
For the EMIF Clock in the first screenshot it is shows the Access Mode of the EMIF is in Sync Mode with a clock out present, it should be connected to the hps2fpg_clk.
If it is in Async Access Mode both hps2fpg_clk and s0_axi4_clk should be connected to the same clock source.
- amsssss123
Hi,
Thank you for the clarification!
I updated the design according to your suggestion:
- emif_io96b_ddr4comp_0.s0_axi4_clock_out -> subsys_hps.hps2fpga_clk
- subsys_hps.h2f_reset -> subsys_hps.hps2fpga_rst
Could you please check whether my current connections are correct, and whether there are any other incorrect parts?
I have one follow-up question about the other HPS bridge clocks. For example, lwhps2fpga_clk is still connected to clk_100 in my design. This clock is used for lightweight HPS-to-FPGA accesses, such as CSR/control registers, not for the main EMIF s0_axi4 data path.
Is it okay for lwhps2fpga_clk and other unrelated HPS-side control clocks to remain on clk_100, even though hps2fpga_clk is now driven by emif_io96b_ddr4comp_0.s0_axi4_clock_out and therefore has a different frequency?
Thank you again for your help!- tehjingy_Altera
Hi amsssss123
From the screenshot, the connections looks okay.
For the lwhps2fpga_clk, it could be connected to the clk_100 when the hps2fpga_clk is connected to a different clock.
- amsssss123
Thank you very much for your help!
