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MarekK's avatar
MarekK
Icon for New Contributor rankNew Contributor
10 months ago

Agilex 5 SLVS-400 Outputs

Dear Altera,

DS for Agilex 5 devices lists SLVS 400 standard among available HSIO bank IO standards. DS specifies voltage levels for both input and output mode and in OCT section both parallel and serial (used for outputs I suppose) termination are specified. So I concluded HSIO banks are capable of SLV400 outputs.

SLVS400 is not mentioned by PHY Lite, it is specified as input only for LVDS Serdes and cannot be assigned to GPIO output.

How can I implement SLVS400 output on Agilex 5 HSIO bank?

Best regards

Marek

Generic Io

5 Replies

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    10 months ago

    Hello Marek,


    Here, if you are referring to the GPIO User Guide for Agilex 5, it is mentioned in footnote 3 that the SLVS-400 unfortunately does not support GPIO mode.


    Regards,

    Aqid


    • MarekK's avatar
      MarekK
      Icon for New Contributor rankNew Contributor
      10 months ago

      Hello Aqid,

      thanks for your answer, but it seems you didn't understand my question, so I will try to rephrase it.

      DS (datasheet for Agilex 5 DS-813918 | 2025.01.23) on page 48 in Table 38 specifies Vod and Vocm for SLVS400 standard. Vod an Vocm are (based on Table 114 on page 172) output parameters - diff. swing and common mode voltage. From this I conclude, that Agilex 5 HSIO bank is capable of SLVS400 output functionality. Is that conclusion correct?

      I was able to find three ways of using IOs of Agilex 5 in quartus - via LVDS Serdes, via PHY Lite and as GPIO. As I already mentioned I studied documentation and found that PHY Lite doesn't mention SLVS400 at all, LVDS Serdes can implement only inputs in SLVS400 standard and (as you verified) GPIO mode doesn't support SLVS400 mode. So my second question: How can I implement SLVS400 output?

      Is now clear what I am asking about?

      Thanks

      Marek

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    9 months ago

    Hello Marek,


    I understand your concern now.

    I am checking with the internal team, we recognized that MIPI TX usage will utilize SLVS buffers.


    Regards,

    Aqid


  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    9 months ago

    Since there are no feedback for this case, I shall set this case to close pending. If you still need further assistance, you are welcome reopen this case within 20days or open a new case, someone will be right with you.


    • MarekK's avatar
      MarekK
      Icon for New Contributor rankNew Contributor
      9 months ago

      Hello AqidAyman_Intel,

      There is no feedback from me for last twenty days, because you told me you are checking the problem with your team. So I expected you get back to me and give me any relevant information. If the half sentence "we recognized that MIPI TX usage will utilize SLVS buffers" was meant as a final solution, please state it clearly. It doesn't seem like solution to me. MIPI TX may use internally SLVS buffers(as far as I know this is never said directly in the doc), but it uses DPHY standard that is specified separately in the DS.

      Regards

      Marek