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MarekK's avatar
MarekK
Icon for New Contributor rankNew Contributor
1 year ago

Agilex 5 SLVS-400 Outputs

Dear Altera, DS for Agilex 5 devices lists SLVS 400 standard among available HSIO bank IO standards. DS specifies voltage levels for both input and output mode and in OCT section both parallel and s...
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Since there are no feedback for this case, I shall set this case to close pending. If you still need further assistance, you are welcome reopen this case within 20days or open a new case, someone will be right with you.


  • MarekK's avatar
    MarekK
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hello AqidAyman_Intel,

    There is no feedback from me for last twenty days, because you told me you are checking the problem with your team. So I expected you get back to me and give me any relevant information. If the half sentence "we recognized that MIPI TX usage will utilize SLVS buffers" was meant as a final solution, please state it clearly. It doesn't seem like solution to me. MIPI TX may use internally SLVS buffers(as far as I know this is never said directly in the doc), but it uses DPHY standard that is specified separately in the DS.

    Regards

    Marek