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glen-7's avatar
glen-7
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8 days ago

Agilex 5: LPDDR5 T-line routing for 1CH x 32 configuration

My question is regarding the requirement for T-line routing when connecting a LPDDR5 memory IC to an Agilex-5 FPGA, using the 1CHx2 configuration. We are using A5EC043AB32AE2V with a single instance...
Programmable Logic Device
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 days ago

Hi glen-7 ,

 

  1. Do you have any reference designs which use the T-line routing style like Figure 32 that I could use as a guide?
    1. I think you may refer to the board design from Agilex 5 devkit or Agilex 7 M devkit.
  2. Is there any subject matter experts at the factory who might have some advice on this routing topology?
    1. You may ask the question and I will try to help on that.
  3. Is it possible to use a daisy-chain routing style for the WCK, CK, and CA traces, instead of t-line?
    1. Yes it's possible. You may refer to this document for the PCB layout guideline: https://docs.altera.com/r/docs/821801/current/pcb-design-guidelines-hssi-emif-mipi-true-differential-pdn-user-guide-agilextm-5-fpgas-and-socs/lpddr5-interface-design-guidelines

 

Regards,

Adzim