agilex 5 lpddr4 connection

Hi Dany,

Are you looking for the layout file for LPDDR4 in Agilex 5? If yes, please find the user guide here

7.3. LPDDR4 Layout Design Guidelines - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-1-6-1-0/lpddr4-layout-design-guidelines.html

7.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR4 - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-1-6-1-0/fpga-emif-ip-parameter-for-lpddr4.html

8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-3-1/fpga-emif-ip-pin-and-resource-planning-80533.html

Thanks

Best regards,

Khai

Hi Dany,

I hope my previous reply was helpful. Please do not hesitate to reach out if you have any further questions.

Thanks

Best regards,

Khai

Hi Dany,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thanks.

Best regards,

Khai