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Dany2's avatar
Dany2
Icon for New Contributor rankNew Contributor
1 year ago

agilex 5 lpddr4 connection

Hi guys I have to design a board with the agilex 5, and lpddr4. The configuration is similar to the agilex 5 premium evaluation kit (two 16 bit channels connected to the single 32 bit). CA/CS/CLK s...
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KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi Dany,


Are you looking for the layout file for LPDDR4 in Agilex 5? If yes, please find the user guide here


7.3. LPDDR4 Layout Design Guidelines - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-1-6-1-0/lpddr4-layout-design-guidelines.html


7.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR4 - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-1-6-1-0/fpga-emif-ip-parameter-for-lpddr4.html


8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-3-1/fpga-emif-ip-pin-and-resource-planning-80533.html


Thanks

Best regards,

Khai