ADC0804 interfaced with CPLD

The ADC0804 is a pretty slow ADC (100us conversion time). Its basically designed for measuring DC values.

From a brief look at the data sheet

http://www.ti.com/product/adc0804

It says you can treated the interface like a microprocessor I/O device. The timing diagrams show that the read/write interface is essentially asynchronous, you just have to assert the signals for as long as the data sheet indicates - based on how you clock the thing. Since the clock is so slow and the ADC dynamic range is only 8-bits (so clock jitter is not so important), you can generate the clock using the CPLD.

Do you have a board that already contains the part, or are you just creating a proto-board interface?

Cheers,

Dave

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On most of the circuit diagrams I look at the RC network used to clock the ADC has the following value: C=150 pF and R=10 kohm.

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From the figure in the data sheet, the clock can be generated using an RC network, or you can just drive the clock pin directly from the CPLD. Personally I would drive it from the CPLD, so that you know the exact frequency.

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I am using the matrix multimedia CPLD target board which has a 25 MHz crystal.

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Link?

The ADC is a 5V part. I sure hope your CPLD is 5V tolerant ...

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I have reduced the clock frequency to 625 KHz as read that is the most frequently speed used. I have followed the steps given on the data sheet for starting the conversion and reading the value. No success yet unfortunately. Does what I wrote see correct to you?

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Yes, it sounds fine.

Capture some read/write traces ... you'll have to use an oscilloscope, since you are using a CPLD. If you were using an FPGA, you could use SignalTap. Alternatively, create a testbench and post Modelsim waveforms.

Cheers,

Dave

Dave,

Thanks again, I am sorry the link for the hardware is below.

http://www.matrixmultimedia.com/resources/files/datasheets/eb020-30-3.pdf

I feel better connected the CPLD clock frequency to the ADC. I will have a go at this tomorrow and get some output traces. Before testing it actually on the hardware.

Cheers

Jag.

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Thanks again, I am sorry the link for the hardware is below.

http://www.matrixmultimedia.com/resources/files/datasheets/eb020-30-3.pdf

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The CPLD is powered from 5V, so you can connect this to the ADC ok.

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I feel better connected the CPLD clock frequency to the ADC. I will have a go at this tomorrow and get some output traces. Before testing it actually on the hardware.

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You need to create a slower speed clock in the CPLD and then connect that to the ADC. You would create the slower speed clock using a counter. The counter can be used to count the half-period of the clock you want, and then you toggle the clock output every time the counter completes (asserts carry-out). This gives you a nice square wave for the output clock.

Cheers,

Dave

Dave,

I am a bit confused here, I have already managed to reduced the 25 MHz to 625 KHz using a counter. Is this what you meant or do you mean I have to reduce the 625 KHz further.

Jag.

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I am a bit confused here, I have already managed to reduced the 25 MHz to 625 KHz using a counter. Is this what you meant or do you mean I have to reduce the 625 KHz further.

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You stated in the message above "I feel better connected the CPLD clock frequency to the ADC", so I just wanted to make sure that you knew you needed to use a slower clock. You obviously do, so you're all set!

Cheers,

Dave

Dave,

I should have been more clear, mu fault. Thanks again mate for all your help.

Jag.

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Thanks again mate for all your help.

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No problem! Good luck with your tests.

Cheers,

Dave

Sorry to bother you again Dave.

I can not get me code working, if you can could have a quick look at my code.

-- Standard libary delarations

library ieee;

use ieee.std_logic_1164.all;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- define input and outputs for the entity

--Entity is the device inputs and outputs

entity convert is port(

--input variable (1-bit)

cs: out std_logic:='1';

rd: out std_logic:='1';

wr: out std_logic:='1';

intr: inout std_logic:='1';

digin: in std_logic_vector(7 downto 0);

digout: out std_logic_vector(7 downto 0);

flag: out std_logic;

--buffer can be input or output

conversion: in std_logic);

end convert;

-- internal function of entity

architecture behave of convert is

--internal variable

signal count2: integer range 0 to 50:=1;

--signal count3: integer range 0 to 20:=1;

begin

process (intr,conversion)

begin

-- Required in order to convert the sinewave to a square wave

-- Check for clock to occur and trigger on rising edge

if(conversion'event and conversion='1') then

--increment the count variable by 1

count2<=count2+1;

if(count2 = 4) then

cs<='0';

else

if(count2 = 8) then

wr<='0';

else

if(count2 = 12) then

cs<='1';

else

if(intr='1') then

count2<=count2;

end if;

if(count2 = 20) then

cs<='0';

end if;

if(count2 = 30) then

rd<='0';

digout<=digin;

end if;

if(count2 = 40) then

rd<='1';

end if;

if(count2 = 50) then

cs<='1';

count2 <= 1;

end if;

-- end all the if statements

end if;

end if;

end if;

end if;

--end if;

--end the process

end process;

--end internal function

end behave;

There is another part of the code which reduces the 25 MHz clock signal to 625 KHz. The clock out of that component is connected to conversion input. I have connected the 625 clock frequency to pin 4 of the ADC0804 and checked with Oscilliscope. I have output traces showing that code works but I am getting no outputs. Could you please, please give some advice.

Jag.