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On most of the circuit diagrams I look at the RC network used to clock the ADC has the following value: C=150 pF and R=10 kohm.
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From the figure in the data sheet, the clock can be generated using an RC network, or you can just drive the clock pin directly from the CPLD. Personally I would drive it from the CPLD, so that you know the exact frequency.
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I am using the matrix multimedia CPLD target board which has a 25 MHz crystal.
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Link?
The ADC is a 5V part. I sure hope your CPLD is 5V tolerant ...
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I have reduced the clock frequency to 625 KHz as read that is the most frequently speed used. I have followed the steps given on the data sheet for starting the conversion and reading the value. No success yet unfortunately. Does what I wrote see correct to you?
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Yes, it sounds fine.
Capture some read/write traces ... you'll have to use an oscilloscope, since you are using a CPLD. If you were using an FPGA, you could use SignalTap. Alternatively, create a testbench and post Modelsim waveforms.
Cheers,
Dave
Honored Contributor
