ADC0804 interfaced with CPLD

Sorry to bother you again Dave.

I can not get me code working, if you can could have a quick look at my code.

-- Standard libary delarations

library ieee;

use ieee.std_logic_1164.all;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- define input and outputs for the entity

--Entity is the device inputs and outputs

entity convert is port(

--input variable (1-bit)

cs: out std_logic:='1';

rd: out std_logic:='1';

wr: out std_logic:='1';

intr: inout std_logic:='1';

digin: in std_logic_vector(7 downto 0);

digout: out std_logic_vector(7 downto 0);

flag: out std_logic;

--buffer can be input or output

conversion: in std_logic);

end convert;

-- internal function of entity

architecture behave of convert is

--internal variable

signal count2: integer range 0 to 50:=1;

--signal count3: integer range 0 to 20:=1;

begin

process (intr,conversion)

begin

-- Required in order to convert the sinewave to a square wave

-- Check for clock to occur and trigger on rising edge

if(conversion'event and conversion='1') then

--increment the count variable by 1

count2<=count2+1;

if(count2 = 4) then

cs<='0';

else

if(count2 = 8) then

wr<='0';

else

if(count2 = 12) then

cs<='1';

else

if(intr='1') then

count2<=count2;

end if;

if(count2 = 20) then

cs<='0';

end if;

if(count2 = 30) then

rd<='0';

digout<=digin;

end if;

if(count2 = 40) then

rd<='1';

end if;

if(count2 = 50) then

cs<='1';

count2 <= 1;

end if;

-- end all the if statements

end if;

end if;

end if;

end if;

--end if;

--end the process

end process;

--end internal function

end behave;

There is another part of the code which reduces the 25 MHz clock signal to 625 KHz. The clock out of that component is connected to conversion input. I have connected the 625 clock frequency to pin 4 of the ADC0804 and checked with Oscilliscope. I have output traces showing that code works but I am getting no outputs. Could you please, please give some advice.

Jag.