ADC output from LVDS deserializer.

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is it called DPA (dynamic shift alignment) ? how do we activate this function? cause last time i check with altlvds_rx in Megawizard, it was grayed out, and someone in the forum said DPA is not available to Cyclone series.

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DPA is a feature of hardware LVDS_RX blocks in Stratix and Arria FPGA family and allows an automatic sampling phase correction of individual bits under some prerequisites. It's in fact not available with Cyclone FPGAs.

Dynamic phase shift is a basic feature of the PLL blocks since Cyclone III. It can be used to achieve a DPA-like functionality with the LVDS PLL, but not for individual bits. Unlike with hardware DPA, that can be simply enabled in the MegaWizard, you have to design the phase shift state machine and signal edge detector yourself.

@eRen: Your point isn't clear. There's no doubt about wrong bits in the ADC data. The original poster also reported, that he was able to fix the problem. Length mismatch can't explain the failure of individual bits in this case, because it's a serial LVDS data transmission over a single differential pair, so all bits undergo the same delay.

What FvW said is reasonable. Maybe add a NOT gate in outclock will resovle the problem.

What kind of the ADC? AFE5851?AFE5801?

The mismatch may between the clock signal and data signal, or the lvds p and lvds n.

If the mismatch is between the clock and data signals, you can try the method:

HSMC_RX_D_P -> PLL( the output frequency is same as the input, adjusting the phase ) -> LVDS12401 -> DCFIFO

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Dynamic phase shift is a basic feature of the PLL blocks since Cyclone III. It can be used to achieve a DPA-like functionality with the LVDS PLL, but not for individual bits. Unlike with hardware DPA, that can be simply enabled in the MegaWizard, you have to design the phase shift state machine and signal edge detector yourself.

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well.. its good to know it can be done.. but i have absolutely no idea how to do that.

Michael

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If the mismatch is between the clock and data signals, you can try the method:

HSMC_RX_D_P -> PLL( the output frequency is same as the input, adjusting the phase ) -> LVDS12401 -> DCFIFO

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we already talked about that in this thread.. making a timing constraint file to do that phase shifting "expectation".. in order to tell fpga what to expect from ADC.. how much degree of phase shift is data with respect to clock.

Michael