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Altera_Forum's avatar
Altera_Forum
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14 years ago

ADC output from LVDS deserializer.

Hi, I have a an ADC sampling at 40 MHz, and it output LVDS signal, so i have to deserialize it using my DE2-115, but i am having trouble with the deserialized signal (shown in the picture), it ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

If the mismatch is between the clock and data signals, you can try the method:

HSMC_RX_D_P -> PLL( the output frequency is same as the input, adjusting the phase ) -> LVDS12401 -> DCFIFO