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Altera_Forum's avatar
Altera_Forum
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14 years ago

ADC output from LVDS deserializer.

Hi, I have a an ADC sampling at 40 MHz, and it output LVDS signal, so i have to deserialize it using my DE2-115, but i am having trouble with the deserialized signal (shown in the picture), it ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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If the mismatch is between the clock and data signals, you can try the method:

HSMC_RX_D_P -> PLL( the output frequency is same as the input, adjusting the phase ) -> LVDS12401 -> DCFIFO

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we already talked about that in this thread.. making a timing constraint file to do that phase shifting "expectation".. in order to tell fpga what to expect from ADC.. how much degree of phase shift is data with respect to clock.

Michael