Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAccessing HPS Pins
Hello, I know I can route HPS pins to the FPGA side but is it possible to do the opposite, route FPGA side logic to HPS part pins? Thank you
Altera_ForumHonored Contributor
Honored ContributorThat's correct, you will not have access to the I/O flip flops and many of the other features that the FPGA I/O offer like scalable delays. This is not actually a tool issue, the I/O used by the HPS are physically different than the ones on the FPGA side of the Cyclone/Arria V SoC device.
In 13.1 those I/O paths to/from the FPGA and the HPS I/O are not characterized yet. If you need to close timing on those paths you can contact your FAE to request a patch to add this timing information.
