Altera_Forum
Honored Contributor
Honored ContributorAccess to Avalon Memory via VHDL
Does anyone have a simple example of VHDL to access RAM or ROM within an SOPC block? Thanks.
Forum Discussion
5 Replies
Altera_ForumI think there are some Avalon Master templates available somewhere. If not, you can read the Avalon specification to see how to write an Avalon master to access your memory.
- Altera_Forum
if you open the component editor there should be a Avalon MM Master template in the pull down
- Altera_Forum
Thanks Daixiwen, but my knowledge of VHDL is not sufficient to translate the information in the Avalon spec to useful code. For example, do I need to implement complete SPI-based addressing functionality in VHDL simply to read from or write to a specific address?
- Altera_Forum
Fer a simple (non bursted and non pipelined) read or write access, you need to:
[list][*]put the address on the address signal [*]for a read, assert the read signal [*]for a write, put the data on the writedata signal and assert the write signal [*]wait until waitrequest is deasserted [*]deassert read and write. For a read access, the data will be available on readdata [/list] - Altera_Forum
I thought someone posted VHDL master templates somewhere but I can't find them. Here are some old ones in verilog that let you shovel data in/out of an SOPC Builder system from the outside world: http://www.altera.com/support/examples/nios2/exm-avalon-mm.html These are meant for DMA types of accesses but you should be able to use them to move a word of data at a time assuming you don't mind some FIFO latency in your data path.
