Altera_Forum
Honored Contributor
Honored ContributorAccess to Avalon Memory via VHDL
Does anyone have a simple example of VHDL to access RAM or ROM within an SOPC block? Thanks.
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Altera_ForumHonored Contributor
Honored ContributorFer a simple (non bursted and non pipelined) read or write access, you need to:
[list][*]put the address on the address signal [*]for a read, assert the read signal [*]for a write, put the data on the writedata signal and assert the write signal [*]wait until waitrequest is deasserted [*]deassert read and write. For a read access, the data will be available on readdata [/list]
