About PLL_OUT as LVDS clock

I want to generate a 500MHz LVDS clock as the LVDS sampling clock for the ADC by a ALTPLL in EP2S15F484C4.

I followed the example in ug_altpll.pdf downloaded from Altera.

1.Select a dedicated CLK pin such as PIN_AB13,

2.Select input clk frequency as 40MHz,

3.Enable "Setup PLL in LVDS mode" option,Select Date Rate as 1000Mbps,

4.Only select one output clock c0,select the frequency as 500MHz,

5.Select the dedicated PLL OUT pin, PLL6_OUT0p(PIN_AB10),to connect to c0.

But the compiler errors said "Error: Output pin "PLL_60" (external output clock of PLL "PLL5:inst2|altpll:altpll_component|pll") uses I/O standard LVDS, has current strength Maximum Current, output load 0pF, and output clock frequency of 500 MHz, but target device can support only maximum output clock frequency of 400 MHz for this combination of I/O standard, current strength, and load" .

Then Select one nomal LVDS output pin,DIFFIO_TX25p(PIN_J5),to connect to c0.But the errors reports are still same as above.

I tried to find the max LVDS output clock frequency of the PLL_OUT in EP2S15F484C4,but I have not found the right answer.I think if the maximum output clock frequency is 400 MHz,it should tell me that 500MHz is not achievable,but it not.

Could anyone help me?

Many thanks.