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Honored Contributor
Honored ContributorAbout PLL_OUT as LVDS clock
I want to generate a 500MHz LVDS clock as the LVDS sampling clock for the ADC by a ALTPLL in EP2S15F484C4. I followed the example in ug_altpll.pdf downloaded from Altera. 1.Select a dedicated CL...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I just selected EP2S15F484C3 to compile,the compilation report errors are still same as before. I have to select LVDS which is the only one interface I/O standard the ADC uses. --- Quote End --- I got the same result in a test with a row LVDS Tx pair. According to my understanding of the device manual, it should support 500 MHz, but the compiler apparently assumes the same toggle rates as for a dedicated clock output. It seems like a Quartus bug. If you send the clock through a logic gate to the output, e.g. and with a dummy input signal, 500 MHz is accepted.
