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I just selected EP2S15F484C3 to compile,the compilation report errors are still same as before. I have to select LVDS which is the only one interface I/O standard the ADC uses.
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I got the same result in a test with a row LVDS Tx pair. According to my understanding of the device manual, it should support 500 MHz, but the compiler apparently assumes the same toggle rates as for a dedicated clock output. It seems like a Quartus bug.
If you send the clock through a logic gate to the output, e.g. and with a dummy input signal, 500 MHz is accepted.
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