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Altera_Forum
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15 years ago

About PLL_OUT as LVDS clock

I want to generate a 500MHz LVDS clock as the LVDS sampling clock for the ADC by a ALTPLL in EP2S15F484C4. I followed the example in ug_altpll.pdf downloaded from Altera. 1.Select a dedicated CL...
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Altera_Forum
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15 years ago

Great!

Thank you very much.

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I got the same result in a test with a row LVDS Tx pair. According to my understanding of the device manual, it should support 500 MHz, but the compiler apparently assumes the same toggle rates as for a dedicated clock output. It seems like a Quartus bug.

If you send the clock through a logic gate to the output, e.g. and with a dummy input signal, 500 MHz is accepted.

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