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Honored Contributor
Honored ContributorAbout PLL_OUT as LVDS clock
I want to generate a 500MHz LVDS clock as the LVDS sampling clock for the ADC by a ALTPLL in EP2S15F484C4. I followed the example in ug_altpll.pdf downloaded from Altera. 1.Select a dedicated CL...
Altera_ForumHonored Contributor
Honored ContributorRefer to the maximum output toggle rate table in Stratix II handbook. It tells that 500 MHz LVDS should work for row I/O pins, but not for clock outputs.
I wonder, if other differential I/O standards may be applicable for your design?
