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Altera_Forum
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14 years ago

About PLL_OUT as LVDS clock

I want to generate a 500MHz LVDS clock as the LVDS sampling clock for the ADC by a ALTPLL in EP2S15F484C4. I followed the example in ug_altpll.pdf downloaded from Altera. 1.Select a dedicated CL...
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Altera_Forum
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14 years ago

Thank your quick relpy.

PIN_AB10 is column I/O,but PIN_J5 is row one.

I just selected EP2S15F484C3 to compile,the compilation report errors are still same as before.

I have to select LVDS which is the only one interface I/O standard the ADC uses.

Regards.

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Refer to the maximum output toggle rate table in Stratix II handbook. It tells that 500 MHz LVDS should work for row I/O pins, but not for clock outputs.

I wonder, if other differential I/O standards may be applicable for your design?

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