about external pll in lvds_rx and lvds_tx

--- Quote Start ---

i am new to lvds mega in quartus . i wanna know that what is the difference between using internal pll and external pll,since there is an option in the lvds_tx, lvds_rx general pannel. which kind configuration is easier and more stable? and my device is ep2c35.

thanks !

yu.p

--- Quote End ---

Use the internal PLL unless you need to dynamically controller the PLL parameters. The default configuration takes care of the timing analysis constraints.

Cheers,

Dave

--- Quote Start ---

Use the internal PLL unless you need to dynamically controller the PLL parameters. The default configuration takes care of the timing analysis constraints.

Cheers,

Dave

--- Quote End ---

Thanks dave！Our board have been made that the inclk ports are not drawn out. So i cann't use the internal pll of the lvds mega, and the internal pll of lvds mega needs a inlck to feed the pll.

I will try the external pll .

Thanks !

yu.p

--- Quote Start ---

Our board have been made that the inclk ports are not drawn out. So i cann't use the internal pll of the lvds mega, and the internal pll of lvds mega needs a inlck to feed the pll.

I will try the external pll .

--- Quote End ---

The altlvds component with PLL or with external PLL uses the same PLL component within the FPGA. If you have not routed a global clock input on your board, then you are in trouble.

Cheers,

Dave

--- Quote Start ---

The altlvds component with PLL or with external PLL uses the same PLL component within the FPGA. If you have not routed a global clock input on your board, then you are in trouble.

Cheers,

Dave

--- Quote End ---

Thanks ! i know that no matter internal or external plls i used in altlvds, they are the pll in the FPGA. And now, I send the data and the fast clock of altlvds_tx to the altlvds_rx. The connection is tx_inclk ------> rx_inclk, tx_out----------------> rx_in.The altlvds works, but the data received is not right.

Any suggestion to solve the problem ? And could my method work well ?

Thanks dave!

yu.p

--- Quote Start ---

I send the data and the fast clock of altlvds_tx to the altlvds_rx. The connection is tx_inclk ------> rx_inclk, tx_out----------------> rx_in.The altlvds works, but the data received is not right.

Any suggestion to solve the problem ? And could my method work well ?

--- Quote End ---

If you do it right, it will work well.

Have you simulated your design in Modelsim?

Are you sending a frame clock to frame your LVDS data? For example, if you are serializing 8:1, and then deserializing 1:8, you should be sending a frame clock that is 1/8th of the data rate.

Have you ensured that your LVDS receivers have terminations?

Cheers.

Dave

--- Quote Start ---

If you do it right, it will work well.

Have you simulated your design in Modelsim?

Are you sending a frame clock to frame your LVDS data? For example, if you are serializing 8:1, and then deserializing 1:8, you should be sending a frame clock that is 1/8th of the data rate.

Have you ensured that your LVDS receivers have terminations?

Cheers.

Dave

--- Quote End ---

Is the frame clock you mentioned above the tx_syncclock in altlvds?

i send it.And the LVDS have terminations.

--- Quote Start ---

Is the frame clock you mentioned above the tx_syncclock in altlvds?

i send it.And the LVDS have terminations.

--- Quote End ---

You should really read the altlvds MegaCore users guide:

http://www.altera.com/literature/ug/ug_altlvds.pdf

and simulate the component in Modelsim. Getting it to work there will show you what the clocks need to be.

Cheers,

Dave

--- Quote Start ---

You should really read the altlvds MegaCore users guide:

http://www.altera.com/literature/ug/ug_altlvds.pdf

and simulate the component in Modelsim. Getting it to work there will show you what the clocks need to be.

Cheers,

Dave

--- Quote End ---

Thanks Dave!

i have almost tried every option to apply altlvds, i recived the data,but the data and the clock had some phase difference. And at last, I gave up the altlvds, and wrote one by myself. Now ,it works well.

Thanks again!

yu.p