about external pll in lvds_rx and lvds_tx

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The altlvds component with PLL or with external PLL uses the same PLL component within the FPGA. If you have not routed a global clock input on your board, then you are in trouble.

Cheers,

Dave

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Thanks ! i know that no matter internal or external plls i used in altlvds, they are the pll in the FPGA. And now, I send the data and the fast clock of altlvds_tx to the altlvds_rx. The connection is tx_inclk ------> rx_inclk, tx_out----------------> rx_in.The altlvds works, but the data received is not right.

Any suggestion to solve the problem ? And could my method work well ?

Thanks dave!

yu.p