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Honored Contributor
Honored Contributorabout external pll in lvds_rx and lvds_tx
i am new to lvds mega in quartus . i wanna know that what is the difference between using internal pll and external pll,since there is an option in the lvds_tx, lvds_rx general pannel. which kind co...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- If you do it right, it will work well. Have you simulated your design in Modelsim? Are you sending a frame clock to frame your LVDS data? For example, if you are serializing 8:1, and then deserializing 1:8, you should be sending a frame clock that is 1/8th of the data rate. Have you ensured that your LVDS receivers have terminations? Cheers. Dave --- Quote End --- Is the frame clock you mentioned above the tx_syncclock in altlvds? i send it.And the LVDS have terminations.
