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Altera_Forum's avatar
Altera_Forum
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15 years ago

a verilog syntax issue that i can't figure out

i have a verilog design of an sdcontroller which i obtained from opencores and which iam trying to simulate. well its a certified design but its giving one peculiar error. one of the design files when compiled with the following command in modelsim 6.4 se plus gives the error:

# vlog -work work -vopt -sv +incdir+c:/modeltech_6.4/examples/verilog/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/verilog -nocovercells c:/modeltech_6.4/examples/verilog/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/verilog/sd_ip_comp_inst.v

# model technology modelsim se vlog 6.4 compiler 2008.06 jun 18 2008

# ** error: c:/modeltech_6.4/examples/verilog/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/verilog/sd_ip_comp_inst.v(8): near "assign": syntax error, unexpected "assign", expecting "class"

#

PLEASE HELP ME FIGURE OUT WHAT'S WRONG

THE DESIGN FILE HAS BEEN GIVEN BELOW:

`include "sd_defines.v"

wire sd_cmd_oe;

wire sd_cmd_out;

wire sd_dat_oe;

wire [3:0] sd_dat_out;

assign sd_cmd_pad_io = sd_cmd_oe ? sd_cmd_out : 1'bZ ;

assign sd_dat_pad_io = sd_dat_oe ? sd_dat_out : 4'bzzzz ;

sd_controller_fifo_wba SD_CONTROLLER_TOP

(

.wb_clk_i(wb_clk),

.wb_rst_i(wb_rst),

.wb_dat_i(wbs_sds_dat_i),

.wb_dat_o(wbs_sds_dat_o),

.wb_adr_i(wbs_sds_adr_i[7:2]),

.wb_sel_i(wbs_sds_sel_i),

.wb_we_i(wbs_sds_we_i),

.wb_stb_i(wbs_sds_stb_i),

.wb_cyc_i(wbs_sds_cyc_i),

.wb_ack_o(wbs_sds_ack_o),

.sd_cmd_dat_i(sd_cmd_pad_io),

.sd_cmd_out_o (sd_cmd_out ),

.sd_cmd_oe_o (sd_cmd_oe),

.sd_dat_dat_i ( sd_dat_pad_io),

.sd_dat_out_o ( sd_dat_out ) ,

.sd_dat_oe_o ( sd_dat_oe ),

.sd_clk_o_pad (sd_clk_pad_o)

`ifdef SD_CLK_EXT

, .sd_clk_i_pad (sd_clk_i_pad)

`endif

);

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    This code is missing the "module" statement.

    in my opinion the initial lines are missing.

    What is ther in sd_defines.v ?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    This code is missing the "module" statement.

    in my opinion the initial lines are missing.

    no i dont think it has to be a module necessarily. iam new to verilog so iam not sure but ive seen similar code elsewhere. i guess it's some sort of portmapping. in any case this is a certified design. could there be something wrong with the compiler modelsim or some compile option that iam missing. ive already designated it as a system verilog file. see the -sv switch in the compile command above.:)

    ----------------------------------------------------------------------------------------------------------------------------------------------------

    What is ther in sd_defines.v ?

    --- Quote End ---

    `define BIG_ENDIAN

    `define TIME_OUT_TIME 255

    //OBS komihåg Master SEL to 1111 vid port dek

    //`define SIM

    `define SYN

    `define ACTEL

    `ifdef SYN

    `define RESET_CLK_DIV 2

    `define MEM_OFFSET 4

    `endif

    `ifdef SIM

    `define RESET_CLK_DIV 0

    `define MEM_OFFSET 1

    `endif

    //SD-Clock Defines ---------

    //Use bus clock or a seperate external clock?

    `define SD_CLK_BUS_CLK

    //`define SD_CLK_EXT

    // Use internal clock divider?

    `define SD_CLK_STATIC

    //`define SD_CLK_DYNAMIC

    //SD DATA-transfer defines---

    `define BLOCK_SIZE 512

    `define SD_BUS_WIDTH_4

    `define SD_BUS_W 4

    //at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit.

    //Add 18 for crc, endbit and z.

    `define BIT_BLOCK 1044

    `define CRC_OFF 19

    `define BIT_BLOCK_REC 1024

    `define BIT_CRC_CYCLE 16

    //FIFO defines---------------
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    As mentioned above, the said file isn't a verilog design file, because it has no module statement. It rather looks like an instantiation template.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hello

    Looks like you are running the FIFO version of the controller?

    That module is not actual meant to be compiled, its an example how you should instantiate the design it in to you own top module in your design.

    either past it in or do a 'include on you top module and all you need to do is to add the pin out and you are ready to go.

    I haven't tried the FIFO module very much so please be kind to report any problem.

    The FIFO module has no documentation, check the SW/main.c for clues how to interface with it.

    /Adam