Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

a verilog syntax issue that i can't figure out

i have a verilog design of an sdcontroller which i obtained from opencores and which iam trying to simulate. well its a certified design but its giving one peculiar error. one of the design files whe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

As mentioned above, the said file isn't a verilog design file, because it has no module statement. It rather looks like an instantiation template.