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This code is missing the "module" statement.
in my opinion the initial lines are missing.
no i dont think it has to be a module necessarily. iam new to verilog so iam not sure but ive seen similar code elsewhere. i guess it's some sort of portmapping. in any case this is a certified design. could there be something wrong with the compiler modelsim or some compile option that iam missing. ive already designated it as a system verilog file. see the -sv switch in the compile command above.:)
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What is ther in sd_defines.v ?
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`define BIG_ENDIAN
`define TIME_OUT_TIME 255
//OBS komihåg Master SEL to 1111 vid port dek
//`define SIM
`define SYN
`define ACTEL
`ifdef SYN
`define RESET_CLK_DIV 2
`define MEM_OFFSET 4
`endif
`ifdef SIM
`define RESET_CLK_DIV 0
`define MEM_OFFSET 1
`endif
//SD-Clock Defines ---------
//Use bus clock or a seperate external clock?
`define SD_CLK_BUS_CLK
//`define SD_CLK_EXT
// Use internal clock divider?
`define SD_CLK_STATIC
//`define SD_CLK_DYNAMIC
//SD DATA-transfer defines---
`define BLOCK_SIZE 512
`define SD_BUS_WIDTH_4
`define SD_BUS_W 4
//at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit.
//Add 18 for crc, endbit and z.
`define BIT_BLOCK 1044
`define CRC_OFF 19
`define BIT_BLOCK_REC 1024
`define BIT_CRC_CYCLE 16
//FIFO defines---------------
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