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Altera_Forum
Honored Contributor
Honored Contributora verilog syntax issue that i can't figure out
i have a verilog design of an sdcontroller which i obtained from opencores and which iam trying to simulate. well its a certified design but its giving one peculiar error. one of the design files whe...
Altera_ForumHonored Contributor
Honored ContributorThis code is missing the "module" statement.
in my opinion the initial lines are missing. What is ther in sd_defines.v ?
